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--- resistor [2012/07/01 20:17] – [Active area] mcmaster
+++ resistor [2025/08/04 21:23] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
+====== Depletion load ======
+FIXME: compare with analysis at [NMOS logic design], tried to do for enhancement mode and so analysis didn't work out
+Most MOSFETs encountered are enhancement.  In essence a its off if you don't apply any voltage between gate and source and fully on if you apply lots of voltage between drain and source and a little between the gate and source (ie switching a high voltage load).  However, there are also depletion mode transistor which have essentially the opposite behavior: they are normally on with VGS = 0.
+Depletion load PMOS resistor on Intel 4004 (IC images courtesy of Flylogic, mask from http://www.4004.com):
+{{:flylogic:intel_400:pullup_metal_flylogic.png}}
+{{:flylogic:intel_4004:pullup_delayered.png}}
+{{:intel_4004:pullup_mask_cif.png?150}}
+Which translates to the following schematic:
+{{:mcmaster:resistor:pmos_pulldown_sch.png}}
+So the natural question to ask is how do you tell a depletion from an enhancement load MOSFET?  For a non-obfuscated digital design typically only depletion mode transistors have this configuration and are enhancement otherwise.  Like this, once you get into analog all bets are off and you need to be careful.
 ====== Active area ======
@@ Line 31: / Line 52: @@
 ====== Polysilicon ======
+Polysilicon is a so-so conductor and so simply making a long strip of it will create a significant resistance.
 ====== References ======
   - Resistor Fabrication on Semiconductor Wafers: http://www.siliconfareast.com/resistor-fab.htm
+  - http://uvicrec.blogspot.com/2011/09/understanding-intel-4004.html
+  - NMOS logic design: http://www.ittc.ku.edu/~jstiles/312/handouts/section_10_4_NMOS_Logic_Design_package.pdf